1. Field of the Invention
The present invention relates to a CCD solid state image pick-up device of a frame transfer system and an image pick-up apparatus constituted so as to obtain a still image by the use of the solid state image pick-up device.
2. Description of the Related Art
Electronic still cameras using a solid state image pick-up device are used for introducing image information into a computer apparatus such as a personal computer or a word processor. This electronic still camera is constructed so that object images may be photographed as motion images, namely, a continuity of still images in a manner similar to a conventional image pick-up apparatus such as a TV camera, and so that image information of one desired frame may then be extracted out from the images. Usually, in the processing of the image information of such an electronic still camera in order to speed-up processing, the continuous images are reproduced using image signals having a small amount of information which has been reduced and complete signal processing is performed only for the image information of the single frame to be finally extracted.
FIG. 1 is a block diagram showing a construction of the electronic still camera, and FIG. 2 is a timing chart for explaining its operation.
A CCD solid state image pick-up device 1 has a plurality of light receiving pixels arranged in a matrix form and shift registers made to correspond to the light receiving pixels, respectively. The plurality of light receiving pixels generate and accumulate information charges in response to a light which is irradiated to a light receiving surface by a well-known lens mechanism and which corresponds to an object image. The shift register transfers and outputs the information charges accumulated in the light receiving pixels in accordance with a predetermined order. In the solid state image pick-up device 1, a capacitance for accumulating the information charge as a pixel unit is disposed at an output terminal of the shift register. A charge amount of the information charges to be transferred and output is converted into a voltage value and is then taken out, and a voltage signal of the voltage value is output as an image signal Y0(t).
A driving circuit 2 supplies a multiphase vertical transfer clock .phi.v and a multiphase horizontal transfer clock .phi.h to each of the shift registers of the solid state image pick-up device 1. Each shift register receives these clocks, thereby transferring and outputting the information charges accumulated in the plurality of light receiving pixels in accordance with a predetermined order. That is to say, the information charges are transferred from the light receiving pixels to the shift registers of the solid state image pick-up device 1 at a timing in accordance with a vertical sync signal VT, and the information charges are then transferred and output one row by one row at a timing in accordance with a horizontal sync signal HT, whereby the image signal Y0(t) is obtained. A timing control circuit 3 generates the horizontal sync signal HT and the vertical sync signal VT on the basis of a reference clock of a predetermined period and supplies these signals to the driving circuit 2. The horizontal sync signal HT and the vertical sync signal VT are used to decide timings of a horizontal scan and a vertical scan of the solid state image pick-up device 1, and are formed in accordance with a predetermined television system. The timing control circuit 3 also generates a timing signal PC for standardizing the image signal Y0(t) in accordance with the horizontal sync signal HT and vertical sync signal VT and supplies the generated signal to a signal processing circuit 4 which will be described hereinafter. The timing control circuit 3 also responds to an image deciding instruction DI, thereby stopping a continuous imaging operation of the driving circuit 2 and allowing the signal processing circuit 4 to output image data D(n) of a specified frame corresponding to the image signal Y0(t).
The signal processing circuit 4 retrieves the image signal Y0(t) output from the solid state image pick-up device 1, executes various processes such as sample-and-hold and level correction of the image signal Y0(t) in accordance with the timing signal PC to form an image signal Y1(t) corresponding to a predetermined format, and then supplies the thus formed signal to a display 5. This signal processing circuit 4 has an A/D converter and a D/A converter and is constituted so that signal processing may be performed on the image signal Y0(t) as digital data, and, after completion of the predetermined signal processing, the image signal Y0(t) may be returned to the image signal Y1(t) of an analog value and the returned signal may be then supplied to the display 5. Furthermore, when the timing control circuit 3 receives the image deciding instruction DI, the signal processing circuit 4 supplies the digital image data D(n) of one frame formed from the image signal Y0(t) to the outside as a still image output. The display 5 comprises an LCD panel and the like, and continuously displays images photographed by the solid state image pick-up device 1 in accordance with the image signal Y1(t) which is supplied from the signal processing circuit 4. In this connection, subsequent to the image deciding instruction DI, the display 5 displays a still image corresponding to the image data D(n) output as a still image output.
FIG. 3 is a schematic view showing the construction of the CCD solid state image pick-up device 1 of the frame transfer system. FIG. 4 is a timing chart showing relations between the sync signals and transfer clocks for driving the solid state image pick-up device 1. In this drawing, an arrangement of the light receiving pixels is shown in a matrix of 12 rows.times.16 columns only in order to simplify the drawing.
The CCD solid state image pick-up device 1 of the frame transfer system comprises an image pick-up section 1i, a storage section 1s, a horizontal transfer section 1h, and an output section 1d. The image pick-up section 1i is constituted of a plurality of CCD shift registers which are extended in a vertical direction and arranged mutually in parallel. Each bit of these shift registers constitutes the light receiving pixel. A multiphase frame transfer clock .phi.f which is synchronized with the vertical sync signal VT is supplied to this image pick-up section 1i, so that the information charges accumulated in the light receiving pixels during an imaging period are transferred to the storage section 1s at a high speed within a vertical scan blanking period.
The storage section 1s comprises a plurality of CCD shift registers which continues to shift registers of the image pick-up section 1i. Each CCD shift register of the storage section 1s has the same bit number as that of the shift register of the image pick-up section 1i, and the information charges transferred from the light receiving pixels of the image pick-up section 1i are temporarily stored in the bits of the shift registers. The multiphase vertical transfer clock .phi.v synchronized with the vertical sync signal VT and the horizontal sync signal HT is supplied to this storage section 1s, and the information charges are fetched as a frame unit from the image pick-up section 1i. The storage section 1s transfers the fetched information charges to the horizontal transfer section 1h as a row unit within a horizontal scan blanking period.
The horizontal transfer section 1h comprises a single CCD shift register whose bits are connected to outputs of the shift registers of the storage section 1s and receive the information charges transferred and output from the shift registers of the storage section 1s. The multiphase horizontal transfer clock .phi.h synchronized with the horizontal sync signal HT is supplied to the horizontal transfer section 1h. The horizontal transfer section 1h sequentially transfers the information charges transferred and output from the shift registers of the storage section 1s to the output section 1d side in units of one horizontal line.
The output section 1d includes a capacitance for receiving the information charges on the output side of the horizontal transfer section 1h, receives the information charges transferred and output from the horizontal transfer section 1h into the capacitance, and outputs a voltage value corresponding to a charge amount of the received charges. A reset clock .phi.r in accordance with the horizontal transfer clock .phi.h is supplied to the output section 1d. The information charges sequentially transferred and output from the horizontal transfer section 1h are discharged on a pixel unit basis from the capacitance of the output section 1d, so that a voltage value corresponding to the amount of the information charge of each pixel is extracted. A change in voltage value to be output becomes the image signal Y0(t).
As for the solid state image pick-up device 1 of the frame transfer system as mentioned above, since the storage section 1s for temporarily storing the information charges obtained by imaging is separated from the light receiving pixels of the image pick-up section 1i, little leakage of unnecessary charges from the light receiving pixels occurs. Therefore, the solid state image pick-up device of the frame transfer system is suitable for the electronic still camera in which information charges are read out from the solid state image pick-up device at an arbitrary timing, thereby obtaining a still image.
For the foregoing electronic still camera, motion images are formed by successively operating the solid state image pick-up device 1. The user watches the motion images and can extract a desired still image included in the motion images. A high picture quality is not required in the motion image at this time because the motion image is merely used for confirmation by the user. Therefore, ordinarily, an information amount of the image signal Y0(t) is previously set to be small, so that the signal process in the signal processing circuit 4 is simplified. That is to say, the image signal Y0(t) is reduced on a predetermined column or row unit basis at an input stage of the signal processing circuit 4 and the information amount is decreased, so that subsequent various signal processes are simplified, and high-speed processing can thereby be realized.
However, a configuration in which the image signal Y0(t) is reduced and carried to the signal processing circuit 4 creates a problem that a circuit scale of the signal processing circuit 4 is increased and electric power consumption in the sections also increases. The solid state image pick-up device 1 itself of the frame transfer system having the image pick-up section 1i and the storage section is also has a problem that, as compared with a solid state image pick-up device of an interline transfer system in which a vertical transfer section is disposed between columns of light receiving pixels arranged in a matrix form, a chip area is large and manufacturing costs rise.